A High Speed and Low Power 8 Bit × 8 Bit Multiplier Design Using Novel Two Transistor (2T) XOR Gates

The paper proposes a novel design of two transistor (2T) XOR gate and its application to design an 8 bit x 8 bit multiplier. The design explores the essence of suitably biasing the MOS transistor and engineering the threshold voltage of the MOS transistor through appropriate biasing and device geometry. Using the 2T XOR gates, a full adder has been realised. Detailed simulations have been carried out to compare the proposed 2T XOR gate and 6T full adder against the existing XOR gates and full adders available in literature with respect to power delay product (PDP), noise margin and area. A significant improvement of PDP, area and noise margin has been obtained with the 2T XOR gate with respect to the existing XOR gates. An 8 bit x 8 bit multiplier has also been implemented using the design of 6T adder and its performance has been analysed and compared with similar multipliers designed with peer adders design available in literature. Simulation studies have been carried out using UMC 65-nm, 90-nm and 130-nm CMOS process technologies in Cadence Spectre along-with process, voltage and temperature (PVT) variation analysis. The power delay product (PDP) of the proposed multiplier has been found to be as low as 1.854 pJ using UMC 65-nm CMOS process. The design of the 8 bit x 8 bit multiplier has been extended to the design of 8 bit multiply-accumulate (MAC) unit, which has been simulated using 65-nm CMOS process. A delay of 3.977 ns and power dissipation of 1.107 mW has been obtained with the MAC unit. The proposed XOR gate is also evaluated through independent gate (IG) mode FINFETs in 32-nm technology as a substitute to CMOS technology.